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High Definition Audio SoundMAX Codec AD1989B
FEATURES
Ten 192 kHz, 101 dB DACs 7.1 surround sound plus independent headphone All independent sample rates, 8 kHz through 192 kHz Selectable stereo mixer on outputs 16-, 20-, and 24-bit resolution Six 192 kHz, 92 dB ADCs Simultaneous record of up to 3 stereo channels All independent sample rates, 8 kHz through 192 kHz 16-, 20-, and 24-bit resolution S/PDIF output 2 independent transmitters, second S/PDIF can support external HDMI interface Supports 44.1 kHz through 192 kHz sample rates 16-, 20-, and 24-bit data; PCM, and AC3 formats Digital PCM gain control S/PDIF input Supports 44.1 kHz through 192 kHz sample rates 16-, 20-, and 24-bit data; PCM, and AC3 formats Digital PCM gain control Auto synchronizes to source sample rate Dedicated auxiliary pins Stereo CD/auxiliary I/O port w/GND sense MONO_OUT pin for internal speaker with EAPD support Microsoft Vista Premium(R) logo compliant Support up to 9 audio jacks Impedance and presence detection; retasking 5 adjustable microphone bias pins Digital and analog PCBeep 3 general-purpose digital I/O (GPIO) pins Multiple EAPD pins for external circuit control 3.3 V analog and digital supply voltages 1.5 V and 3.3 V HD Audio link signaling Advanced power management modes
S/PDIF Rx S/PDIF Tx S/PDIF Tx DAC4
S/PDIF IN S/PDIF OUT 2 (HDMI) S/PDIF OUT 1 PORT H PORT F PORT G DIGITAL AND ANALOG PCBEEP
H D A U D I O I N T E R F A C E
DAC3 DAC2 DAC1 DAC0
PORT D MONO OUT
PORT E GPIO AND EAPD PORT A PORT B PORT C ADC2
ADC1
ADC0
AD1989B
Figure 1. AD1989B Block Diagram Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
AD1989B
CONTENTS
Features ................................................................. 1 Contents ................................................................ 2 Revision History ...................................................... 2 General Description ................................................. 3 Special Software Features ........................................ 3 Additional Information .......................................... 3 Jack Configuration ................................................ 3 Specifications .......................................................... 4 Test Conditions .................................................... 4 Performance ........................................................ 4 General Specifications ............................................ 4 HD Audio Link Specification ................................... 7 Power-Down States ............................................... 7 Absolute Maximum Ratings .................................... 8 ESD Caution ........................................................ 8 Environmental Conditions ...................................... 8 Pin Configuration and Function Descriptions ................. 9 HD Audio Widgets ................................................ 12 HD Audio Parameters ............................................. 14 Widget Parameters ................................................. 15 Connection List ..................................................... 17 Default Configuration Bytes ..................................... 19 Outline Dimensions ............................................... 20 Ordering Guide ..................................................... 20
REVISION HISTORY
8/08--Revision 0: Initial Version
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AD1989B
GENERAL DESCRIPTION
The AD1989B audio codec and SoundMAX(R) software provides superior HD audio quality that exceeds Vista Premium performance. The AD1989B has ten 101 dB DACs and six 92 dB ADCs, three stereo headphone ports, C/LFE swapping, digital and analog PCBeep, and two independent S/PDIF outputs, making the AD1989B the right choice for PCs where performance and a rich feature set are primary considerations. The jack retasking feature on this product supports various configurations including 7.1 on 5 jacks, 5.1 on 3 jacks, and front panel jack retasking. The AD1989B is available in a 48-lead RoHS compliant lead frame chip scale package in both reels and trays. See Ordering Guide on Page 20.
JACK CONFIGURATION
The guidelines shown in Table 1 and Table 2 should be used when selecting ports for particular functions. Table 1. Typical Desktop Applications with Discreet Jacks (Default Configuration)
Port Port A Port B Port C Port D Port E Port F Port G Port H Function Front Panel Headphone Front Panel Microphone Rear Line-In Rear Line-Out Rear Microphone Rear Surround (5.1) Rear C/LFE Rear Surround (7.1)
SPECIAL SOFTWARE FEATURES
The AD1989B audio codec also supports the following additional software features: * BlackHawk(R) and SoundMAX GUI contain all user audio controls * Voice input enhancement: Andrea Electronics best-in-class noise reduction, beam forming, and echo cancellation * Output enhancement: Sensaura/Sonic Focus, spreading/downmixing, MP3 refinement, adaptive dynamics, compressor/limiter, speaker/graphic EQ, Voice Clarity/ X-MatrixTM, AGC, UI tuning tools * DTS(R), SRS(R), EAX(R) for gaming
Table 2. Typical Desktop Retasking to Support Input/5.1 on 3 Jacks
Port Port A Port B Port C Port D Port E Function Front Panel Headphone Front Panel Microphone Rear Line-In/Surround Out Rear Line-Out Rear Microphone/C/LFE
ADDITIONAL INFORMATION
This data sheet provides a general overview of the AD1989B SoundMAX codec's architecture and functionality. Additional information on the AD1989B is available in the AD1989B Programmers Reference Manual. Please contact your local Analog Devices, Inc., sales representative for more information. For information on SoundMAX codecs and software, see Analog Devices website at http://www.analog.com/soundMAX.
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SPECIFICATIONS
TEST CONDITIONS
Parameter Temperature Digital Supply Analog Supply MIC_BIAS_IN (via Low-Pass Filter) Sample Rate fS Input Signal (Frequency Sine Wave) Amplitude for THD + N Analog Output Pass Band DAC ADC Test Condition 25C 3.3 V 3.3 V 5.0 V 48 kHz 1008 Hz -3.0 dB Full Scale 20 Hz to 20 kHz 10 k Output Load: Line-Out Tests 32 Output Load: Headphone Tests 0 dB Gain
PERFORMANCE
Parameter Line-Out Drive (10 k loads--DAC to Pin) Total Harmonic Distortion (THD + N) Dynamic Range (-60 dB in ref to fS A-Weighted) Signal-to-Noise Ratio Headphone Drive (32 loads--DAC to Pin) Total Harmonic Distortion (THD + N) Dynamic Range (-60 dB in ref to fS A-Weighted) Signal-to-Noise Ratio Input Ports (Mic Boost = 0 dB) Total Harmonic Distortion (THD + N) Dynamic Range (-60 dB in ref to fS A-Weighted) Signal-to-Noise Ratio Min Typ -86 101 101 -84 101 101 -80 92 92 Max Unit dB dB dB dB dB dB dB dB dB
GENERAL SPECIFICATIONS
Parameter DIGITAL DECIMATION AND INTERPOLATION FILTERS--fS = 8 kHz to 96 kHz1 Pass Band Pass-Band Ripple Stop Band Stop-Band Rejection Group Delay Group Delay Variation Over Pass Band ANALOG-TO-DIGITAL CONVERTERS Resolution Gain Error (Full-Scale Span Relative to Nominal Input Voltage)2 Interchannel Gain Mismatch (Difference of Gain Errors) ADC Offset Error1 ADC Crosstalk1 Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) Line Inputs to Other DIGITAL-TO-ANALOG CONVERTERS Resolution Gain Error (Full-Scale Span Relative to Nominal Input Voltage)1 Interchannel Gain Mismatch (Difference of Gain Errors) DAC Crosstalk (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT)1 Min 0 0.6 fS -110 20 0 24 0.2 10 0.5 5 Typ Max 0.4 fS 0.005 Unit Hz dB Hz dB 1/fS s Bits % dB mV dB dB Bits % dB dB
-94 -100 24
-80 10 0.5
-104
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Parameter DAC VOLUMES Step Size (DAC0, DAC1, DAC2, DAC3) Output Gain/Attenuation Range Mute Attenuation of 0 dB Fundamental1 ADC VOLUMES Step Size (ADCSEL-0, ADCSEL-1) PGA Gain/Attenuation Range Mute Attenuation of 0 dB Fundamental1 ANALOG MIXER Signal-to-Noise Reduction (SNR) Input to Output Step Size: All Mixer Inputs Input Gain/Attenuation Range: All Mixer Inputs ANALOG LINE LEVEL OUTPUTS Full-Scale Output Voltage: Line-Out Drive Enabled Output Impedance1 External Load Impedance1 Output Capacitance1 External Load Capacitance1 ANALOG HP DRIVE OUTPUTS Full-Scale Output Voltage: Line-Out Drive Enabled Ports A, B and D (when HP Drive is Enabled) Output Impedance1 External Load Impedance1 Output Capacitance1 External Load Capacitance1 ANALOG INPUTS Input Voltages--Ports A, B, C, or E Mic Boost = 0 dB Input Voltages--Microphone Boost Amplifier, Ports B, C, or E Mic Boost = +10 dB Mic Boost = +20 dB Mic Boost = +30 dB Input Impedance PCBEEP Ports A, B, C, E (Mic Boost = 0 dB) Input Capacitance1 MICROPHONE BIAS MIC_BIAS-B, MIC_BIAS-C MIC_BIAS_IN (Pin 33) = +5 V or +3.3 V Min Typ 1.5 -58.5 -80 1.5 -58.5 -80 95 -1.5 -34.5 1.0 190 10 15 1000 1.0 2.83 0.5 32 15 1000 +12.0 +22.5 0 Max Unit dB dB dB dB dB dB dB dB dB V rms3 k pF pF V rms3 V p-p pF pF
1 2.83 0.316 0.894 0.1 0.283 0.032 0.089 23 150 5
V rms3 V p-p V rms3 V p-p V rms3 V p-p V rms3 V p-p k k pF
7.5
MIC_BIAS_IN (Pin 33) = +5 V MIC_BIAS_IN (Pin 33) = +3.3 V
VREF Setting = High-Z VREF Setting = 0 V VREF Setting = 50% VREF Setting = 80% VREF Setting = 100% VREF Setting = 80% VREF Setting = 100% VREF Setting = High-Z VREF Setting = 0 V VREF Setting = 50% VREF Setting = 80% VREF Setting = 100% VREF Setting = 50%, 80%, or 100%
High-Z 0 1.65 3.7 3.9 2.86 3.0 High-Z 0 1.65 2.86 3.0 1.6
V dc V dc V dc V dc V dc V dc
MIC_BIAS-E (When enabled as BIAS)
V dc V dc V dc V dc mA
Output Drive Current
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Parameter GPIO_0, GPIO_1, and GPIO_2 Input Signal High (VIH) Input Signal Low (VIL) Output Signal High (VOH) IOUT = -500 A Output Signal Low (VOL) IOUT = +1500 A Input Leakage Current (Signal High) (IIH) Input Leakage Current (Signal Low) (IIL) S/PDIF-Out_1, S/PDIF-Out_2 Output Signal High (VOH) IOUT = -500 A Output Signal Low (VOL) IOUT = +1500 A S/PDIF_IN Input Signal High (VIH) Input Signal Low (VIL) Input Leakage Current (Signal High) (IIH) Input Leakage Current (Signal Low) (IIL) POWER SUPPLY Analog (AVDD) 3.3 V 5% Power Supply Range Power Dissipation Supply Current Digital (DVDD) 3.3 V 10% Power Supply Range Power Dissipation Supply Current Digital I/O (DVIO) 3.3 V 10% Power Supply Range Power Dissipation Supply Current Digital I/O (DVIO) 1.5 V 5.5% Power Supply Range Power Dissipation Supply Current Digital GPIO (DVGPIO) 3.3 V 10% Power Supply Range Power Dissipation Supply Current Power Supply Rejection (Reference to fS 100 mV p-p Signal @ 1 kHz)1
1 2
Min DVGPIO x 0.60 0 DVGPIO x 0.72 0
Typ
Max DVGPIO DVGPIO x 0.24 DVGPIO DVGPIO x 0.10
Unit V V V V nA A
-150 -50 DVGPIO x 0.72 0 DVGPIO x 0.60 0 150 -50
DVGPIO V DVGPIO x 0.10 V DVGPIO V DVGPIO x 0.24 V nA A
3.13
3.30 162 49 3.30 241 73 3.30 0.66 0.20 1.50 0.03 0.20 3.30 3.63 1.10 80
3.46
V mW mA V mW mA V mW mA V mW mA V mW mA dB
2.97
3.63
2.97
3.63
1.42
1.58
2.97
3.63
Guaranteed but not tested. Measurements reflect main ADC. 3 RMS values assume sine wave input.
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HD AUDIO LINK SPECIFICATION
HD Audio signals comply with the High Definition Audio Specifications. Please refer to these specifications at: http://www.intel.com/standards/hdaudio/
POWER-DOWN STATES
Parameter Function Node in D0, All Nodes Active Function Node in D3 Codec in RESET Individual Block Power Savings DAC Pair Powered Down Saves (Each) ADC Pair Powered Down Saves (Each) Mixer Power Control (and Associated Amps) Saves MIC_BIAS Powered Down Saves1, 2
1 2
IDVDD Typ 73 24 3 6 6 0 0
IAVDD Typ 49 1 3 5 3 2 0.1
Unit mA mA mA mA mA mA mA
Powering down the MIC_BIAS powers down all port MIC_BIAS pins. This disables all microphone bias circuits, setting them to the high-Z state. Test conditions: 30 pF load, 2.0 MHz frequency, 3.3 V AVDD.
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ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed below may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameter Digital (DVDD) Digital I/O (DVIO) Digital GPIO (DVGPIO) Analog (AVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature Rating -0.30 V to +3.65 V -0.30 V to +3.65 V -0.30 V to +3.65 V -0.30 V to +3.65 V 10.0 mA -0.30 V to AVDD + 0.3 V -0.30 V to DVIO + 0.3 V 0C to +70C -65C to +150C
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating TAMB = TCASE - (PD x CA) TCASE = Case Temperature in C PD = Power Dissipation in W CA = Thermal Resistance (Case-to-Ambient) JA = Thermal Resistance (Junction-to-Ambient) JC = Thermal Resistance (Junction-to-Case) All measurements per EIA-JESD51 with 2S2P test board per EIA-JESD51-7. Table 3. Thermal Resistance
Package LFCSP_VQ JA 47 JC 15 CA 32 Unit C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
S/PDIF-OUT_1/GPIO_2
MONO_OUT
PORT-H_R
PORT-A_R
PORT-G_L
PORT-H_L
PORT-A_L
48 DVCORE S/PDIF-OUT_2/GPIO_0 DVGPIO DVIO SDATA_OUT BIT_CLK DVSS SDATA_IN DVDD SYNC RESET PCBEEP 1 2 3 4 5 6
47
46
45
44
43
42
41
40
39
AVDD
38
MIC_BIAS_A/EAPD-A
S/PDIF_IN/GPIO_1
PORT-G_R
AVSS
37 36 35 34 33 32 31 PORT-D_R PORT-D_L SENSE_B/SRC_A MIC_BIAS_IN MIC_BIAS-D/EAPD-D MIC_BIAS-E/EAPD-E SENSE_C MIC_BIAS-C/EAPD-C MIC_BIAS-B/EAPD-B VREF_FLT AVSS AVDD
AD1989BJCPZ
TOP VIEW
7 (Not To Scale) 8 9 10 11 12 13
SENSE_A/SRC_B
30 29 28 27 26 25
14
PORT-E_L
15
PORT-E_R
16
PORT-F_L
17
PORT-F_R
18
CD_L/LINE_IN_L
19
CD_GND
20
CD_R/LINE_IN_R
21
PORT-B_L
22
PORT-B_R
23
PORT-C_L
24
PORT-C_R
Figure 2. AD1989B 48-Lead Package and Pinout
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Table 4. Pin Function Descriptions
Mnemonic DIGITAL INTERFACE SDATA_OUT BIT_CLK SDATA_IN SYNC RESET DIGITAL I/O S/PDIF-OUT_2/GPIO_0 S/PDIF_IN/GPIO_1 S/PDIF-OUT_1/GPIO_2 JACK SENSE SENSE_A/SRC_B SENSE_B/SRC_A SENSE_C ANALOG I/O PCBEEP Port-E_L Port-E_R Port-F_L Port-F_R CD_L/LINE_IN_L CD_GND CD_R/LINE_IN_R Port-B_L Port-B_R Port-C_L Port-C_R Port-D_L Port-D_R Port-A_L MONO_OUT Port-A_R Port-G_L Port-G_R Port-H_L Port-H_R FILTER/REFERENCE MIC_BIAS-B/EAPD-B MIC_BIAS-C/EAPD-C MIC_BIAS-E/EAPD-E MIC_BIAS-D/EAPD-D MIC_BIAS-A/EAPD-A Pin No. 5 6 8 10 11 2 47 48 13 34 30 12 14 15 16 17 18 19 20 21 22 23 24 35 36 39 40 41 43 44 45 46 28 29 31 32 37 Function I I I/O I I I/O I/O I/O I/O I/O I LI LI, MIC, LO, SWAP LI, MIC, LO, SWAP LO LO LI LI LI LI, MIC, HP, LO LI, MIC, HP, LO LI, MIC, LO LI, MIC, LO LI, HP, LO LI, HP, LO LI, MIC, HP, LO LO LI, MIC, HP, LO LO, SWAP LO, SWAP LO LO O O O O O Description Link Serial Data Output. Clocked on both edges of BIT_CLK. Link Bit Clock. 24.000 MHz serial data clock. Link Serial Data Input. AD1989B output stream clocked only on one edge of BIT_CLK. Link Frame Sync. Link Reset. Master hardware reset. S/PDIF Out or GPIO. Supports S/PDIF output as primary function. S/PDIF Input/General-Purpose Input/Output Pin. Supports S/PDIF input as primary function. S/PDIF_OUT or GPIO. Supports S/PDIF output as primary function. JACK Sense A-D Input/Sense B drive. JACK Sense E-H Input/Sense A drive. JACK Sense CD/Line inputs. Monaural Input From System for Analog PCBeep. Auxiliary Input/Output Left Channel. Auxiliary Input/Output Right Channel. Auxiliary Input/Surround Rear (5.1) Left Channel. Auxiliary Input/Surround Rear (5.1) Right Channel. CD Audio Left Channel. CD Audio Analog Ground Reference (for Differential CD Input). Must be connected to AGND via 0.1 F capacitor if not in use as CD_GND. CD Audio Right Channel. Front Panel Stereo MIC/Line-In. Front Panel Stereo MIC/Line-In. Rear Panel Stereo MIC/Line-In. Rear Panel Stereo MIC/Line-In. Rear Panel Headphone/Line-Out. Rear Panel Headphone/Line-Out. Front Panel Headphone/Line-Out. Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone. Front Panel Headphone/Line-Out. Rear Panel C/LFE Output. Rear Panel C/LFE Output. Rear Panel Surround Center/Side (7.1). Rear Panel Surround Center/Side (7.1).
Switchable Microphone Bias. For use with Port B (Pins 21, 22). Switchable Microphone Bias. For use with Port C (Pins 23, 24). Switchable Microphone Bias. For use with Port E (Pins 14, 15). Switchable Microphone Bias. For use with Port D (Pins 35, 36) Switchable Microphone Bias. For use with Port A (Pins 39, 41) All MIC_BIAS pins are capable of: High-Z, 0 V, 1.65 V, 3.78 V, and 3.95 V (with 5.0 V on Pin 33) High-Z, 0 V, 1.65 V, 2.86 V, and 3.00 V (with 3.3 V on Pin 33). 27 O VREF_FILT Voltage Reference Filter. 1 O DVCORE CAUTION: DO NOT APPLY 3.3 V TO THIS PIN! Filter connection for internal core voltage regulator. This pin must be connected to filter caps: 10 F, 1.0 F, and 0.1 F connected in parallel between Pin 1 and DVSS (Pin 4). The symbols used in this table are defined as: I = input, O = output, LI = line level input, LO = line level output, HP = output capable of driving headphone load, MIC = input supports microphones with MIC bias and boost amplifier, SWAP = outputs can swap L/R channels (typically used to support C/LFE or shared C/LFE function).
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Table 4. Pin Function Descriptions (Continued)
Mnemonic POWER AND GROUND DVGPIO 3.3 V 10% DVIO 3.3 V 10% or DVIO 1.5 V 5.5% DVSS DVDD 3.3 V 10% Pin No. 3 4 Function I I Description GPIO and S/PDIF Out (1 and 2) Signal Level (independent of DVIO). Connect to 3.3 V 10%. Connect to the I/O voltage used for the HD Audio controller signals.
Digital Supply Return (Ground). Digital Supply Voltage 3.3 V. This is regulated down to Pin 1 to supply the internal digital core. AVDD 3.3 V 5% 25, 38 I CAUTION: DO NOT APPLY 5.0 V TO THESE PINS! Analog Supply Voltage 3.3 V ONLY. Note: AVDD supplies should be well regulated and filtered as supply noise degrades audio performance. MIC_BIAS_IN 33 I Source for Microphone Bias Circuitry. Connect this pin to 5.0 V via a low-pass filter. When connected this way the AD1989B is capable of providing +3.95 V as a mic bias to all of the MIC_BIAS pins. If 5 V is not available, connect this pin to +3.3 V (AVDD) via a low-pass filter. The AD1989B produces a mic bias voltage relative to the AVDD supply (typically 3.0 V @ AVDD = 3.3 V). 26, 42 I Analog Supply Return (Ground). AVSS should be connected to DVSS using a AVSS conductive trace under, or close to, the AD1989B. The symbols used in this table are defined as: I = input, O = output, LI = line level input, LO = line level output, HP = output capable of driving headphone load, MIC = input supports microphones with MIC bias and boost amplifier, SWAP = outputs can swap L/R channels (typically used to support C/LFE or shared C/LFE function).
7 9
I I
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HD AUDIO WIDGETS
Table 5. HD Audio Widgets1
Node ID 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2F 30 31 32 33 34 36 Name ROOT FUNCTION S/PDIF_1 DAC DAC_0 DAC_1 DAC_2 DAC_3 S/PDIF ADC ADC_0 ADC_1 DAC_4 S/PDIF_2 DAC ADC Selector 0 ADC Selector 1 ADC Selector 2 ADC_2 Digital Beep Port A (Headphone) Port D (Front L/R) Mono Out Port B (Front Mic) Port C (Line In) Port F (Surr Back) Port E (Rear Mic) CD In/Line In Mixer Power Down Analog PCBeep S/PDIF Out_1 S/PDIF In S/PDIF Out_2 Mono Out Mixer Analog Mixer Mixer Output Atten Port A Mixer VREF Power Down Port G (C/LFE) Port H (Surr Side) Port E Mixer Port G Mixer Port H Mixer Port D Mixer Port F Mixer Port B Mixer Port C Mixer Stereo Mix Down BIAS Power Down Port B Out Selector Port C Out Selector Port E Out Selector Port C In Selector Port E In Selector Mono Out Selector Type ID x x 0 0 0 0 0 1 1 1 1 0 3 3 3 3 7 4 4 4 4 4 4 4 4 5 4 4 4 4 2 2 3 2 F 4 4 2 2 2 2 2 2 2 2 F 3 3 3 3 3 3 Type Root Function Audio Output Audio Output Audio Output Audio Output Audio Output Audio Input Audio Input Audio Input Audio Output Audio Output Audio Selector Audio Selector Audio Selector Audio Input Beep Generator Pin Complex Pin Complex Pin Complex Pin Complex Pin Complex Pin Complex Pin Complex Pin Complex Power Widget Pin Complex Pin Complex Pin Complex Audio Mixer Audio Mixer Audio Mixer Audio Selector Audio Mixer Vendor Defined Pin Complex Pin Complex Audio Mixer Audio Mixer Audio Mixer Audio Mixer Audio Mixer Audio Mixer Audio Mixer Audio Mixer Vendor Defined Audio Selector Audio Selector Audio Selector Audio Selector Audio Selector Audio Selector Description Device identification Designates this device as an audio codec S/PDIF-1 digital stream output interface Headphone/surround side (7.1) channel digital/audio converters Stereo front channel digital/audio converters Stereo C/LFE channel digital/audio converters Stereo surround-back (5.1) channel digital/audio converters S/PDIF digital stream input interface Stereo record Channel 1 audio/digital converters Stereo record Channel 2 audio/digital converters Stereo surround side (7.1) channel digital/audio converters S/PDIF-2 output (typically used for HDMI) Selects and amplifies/attenuates the input to ADC0 Selects and amplifies/attenuates the input to ADC1 Selects and amplifies/attenuates the input to ADC2 Stereo record channel 2 audio/digital converters Internal digital PCBeep signal Front panel headphone/microphone jack Rear panel output/headphone output Monaural output pin (internal speakers or telephony system) Front panel microphone/headphone jack Line-in jack (rear or front) Rear panel surround-rear (5.1) jack Rear panel mic jack Analog CD input or line input Powers down the analog mixer and associated amps External analog PCBeep signal input S/PDIF_1 output pin S/PDIF input pin S/PDIF_2 output pin Selects which source drives the mono out signal Mixes individually gainable analog inputs Attenuates the mixer output to drive the port mixers Mixes the Port A Selected DAC and mixer output amps to drive Port A Powers down the Internal and external VREF circuitry Rear panel C/LFE jack Rear panel surround-side (7.1) jack Mixes DAC4 and mixer output amps to drive Port E Mixes DAC2 and mixer output amps to drive Port G Mixes DAC0 and mixer output amps to drive Port H Mixes DAC1 and mixer output amps to drive Port D Mixes DAC3 and mixer output amps to drive Port F Mixes the Port B selected DAC and mixer output amps to drive Port B Mixes the Port C selected DAC and mixer output amps to drive Port C Mixes the stereo L/R channels to drive mono output Powers down the internal MIC_BIAS_FILT and all MIC_BIAS Pins Selects the Port B DAC (0, 1) Selects the Port C DAC (0, 3) Selects the Port E DAC (2, 4) Selects from the Port C, G, and H inputs to drive the mixer input Selects from the Port E, G, and H inputs to drive the mixer input Selects the mono out DAC (0, 1, 3)
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Table 5. HD Audio Widgets1 (Continued)
Node ID 37 38 39 3A 3C 3D
1
Name Port A Selector Port A Boost Port B Boost Port C Boost Port E Boost Port D Boost
Type ID 3 3 3 3 3 3
Type Audio Selector Audio Selector Audio Selector Audio Selector Audio Selector Audio Selector
Description Selects the Port A DAC (0, 1, 3) Microphone boost amp for Port A Microphone boost amp for Port B Microphone boost amp for Port C Microphone boost amp for Port E Microphone boost amp for Port D
All node IDs (NIDs) are sequential in the codec. Any NIDs missing from this table are vendor defined.
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HD AUDIO PARAMETERS
Table 6. Root and Function Node Parameters
Vendor ID 00 11D4989B Revision ID 021 03 00100300 Sub Node Count 04 00010001 0002003C Func. Group Audio F.G. Type Caps 05 08 00000001 00010C0C GPIO Caps 11 40000003
Node ID 00 01
1
Name ROOT FUNCTION
01
Subject to change with silicon stepping.
Table 7. SubSystem ID 1
Node ID 01
1
Name FUNCTION
Value BFD80000
31:16 SSID BFD8
15:8 SKU 00
7:0 ASM ID 00
The default SSID is overwritten by platform BIOS after power on. It is preserved across HD Audio link reset and verb reset.
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WIDGET PARAMETERS
Table 8. Widget Parameters
Node ID 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2F 30 31 32 33 34 Widget Capabilities 09 0x0000 0480 0x0003 0211 0x0000 0405 0x0000 0405 0x0000 0405 0x0000 0405 0x0013 0391 0x0010 0501 0x0010 0501 0x0000 0405 0x0030 0211 0x0030 010D 0x0030 010D 0x0030 010D 0x0010 0501 0x0070 000C 0x0040 018D 0x0040 018D 0x0040 010C 0x0040 018D 0x0040 018D 0x0040 018D 0x0040 098D 0x0040 0081 0x0050 0500 0x0040 0000 0x0040 030D 0x0040 020B 0x0040 030D 0x0020 0103 0x0020 010B 0x0030 010D 0x0020 0103 0x00F0 0100 0x0040 098D 0x0040 018D 0x0020 0103 0x0020 0103 0x0020 0103 0x0020 0103 0x0020 0103 0x0020 0103 0x0020 0103 0x0020 0100 0x00F0 0100 0x0030 0101 0x0030 0101 0x0030 0101 0x0030 0101 0x0030 0101 PCM Size, Rate 0A 0x000E 07FF 0x000E 07E0 0x000E 07FF 0x000E 07FF 0x000E 07FF 0x000E 07FF 0x000E 07E0 0x000E 07FF 0x000E 07FF 0x000E 07FF 0x000E 07E0 Stream Formats 0B 0x0000 0001 0x0000 0005 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0005 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0005 Pin Capabilities 0C Input Amp Capabilities 0D 0x8000 0000 ConnList Length 0E 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0000 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0000 0x0000 0000 0x0000 0008 0x0000 0007 0x0000 0007 0x0000 0001 0x0000 0000 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0000 0x0000 0002 0x0000 0000 0x0000 0001 0x0000 0000 0x0000 0001 0x0000 0002 0x0000 0008 0x0000 0001 0x0000 0002 0x0000 0008 0x0000 0001 0x0000 0001 0x0000 0002 0x0000 0002 0x0000 0002 0x0000 0002 0x0000 0002 0x0000 0002 0x0000 0002 0x0000 0001 0x0000 0006 0x0000 0003 0x0000 0002 0x0000 0002 0x0000 0003 0x0000 0003 Power States 0F 0x0000 0009 0x0000 0009 0x0000 0009 0x0000 0009 0x0000 0009 0x0000 0009 0x0000 0009 0x0000 0009 Output Amp Capabilities 12 0x0005 2727 0x0005 2727 0x0005 2727 0x0005 2727 0x0005 2727
0x0005 2727 0x8005 3627 0x8005 3627 0x8005 3627
0x000E 07FF
0x0000 0001 0x0000 373F 0x0000 373F 0x0000 0010 0x0000 373F 0x0000 3737 0x0000 0037 0x0000 3737 0x0000 0024 0x0000 0020 0x0000 0010 0x0000 0020 0x0000 0010
0x0000 0009 0x800B 0F0F 0x8000 0000 0x8000 0000 0x8005 1F1F 0x8000 0000 0x8000 0000 0x8000 0000 0x8000 0000 0x0000 0009 0x8005 2727 0x8005 2727
0x8005 1F17 0x8000 0000 0x8005 1F17 0x8000 0000
0x8005 1F1F
0x0000 0037 0x0000 0037 0x8000 0000 0x8000 0000 0x8000 0000 0x8000 0000 0x8000 0000 0x8000 0000 0x8000 0000
0x8000 0000 0x8000 0000
Rev. 0 |
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August 2008
AD1989B
Table 8. Widget Parameters (Continued)
Node ID 36 37 38 39 3A 3C 3D Widget Capabilities 09 0x0030 0101 0x0030 0101 0x0030 010D 0x0030 010D 0x0030 010D 0x0030 010D 0x0030 010D Stream PCM Size, Rate Formats 0A 0B Pin Capabilities 0C Input Amp Capabilities 0D ConnList Length 0E 0x0000 0003 0x0000 0003 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 0x0000 0001 Power States 0F Output Amp Capabilities 12
0x0027 0300 0x0027 0300 0x0027 0300 0x0027 0300 0x0027 0300
Rev. 0 |
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August 2008
AD1989B
CONNECTION LIST
Table 9. Connection List
Connections Node ID 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2F 30 31 32 33 34 36 [0-3] [4-7] 0 NID I 1 NID I 2 NID I 3 NID I 4 NID I 5 NID I 6 NID I 7 NID
0x0000 001C 0x0000 000C 0x0000 000D
0x1C 0x0C 0x0D
0x2418 BC38 0x2418 BC38 0x2418 BC38 0x0000 000E 0x0000 0022 0x0000 0029 0x0000 002D 0x0000 002B 0x0000 002C 0x0000 002A 0x0000 0026 0x0000 2120 0x0000 0002 0x0000 000B 0x0000 2136 0x3D38 3339 0x0000 0020 0x0000 2137 0x2524 9811 0x0000 0027 0x0000 0028 0x0000 2132 0x0000 2105 0x0000 210A 0x0000 2104 0x0000 2106 0x0000 2130 0x0000 2131 0x0000 001E 0x1514 1211 0x0060 0403 0x0000 0A04 0x0000 0405 0x0024 253A 0x0024 253C 0x0006 0403
0x1F20 3D25 0x0020 3D25 0x0020 3D25
0x38 1 0x38 1 0x38 1 0x0E 0x22 0x29 0x2D 0x2B 0x2C 0x2A 0x26 0x20 0x02 0x0B 0x36 0x39 0x20 0x37 0x11 1 0x27 0x28 0x32 0x05 0x0A 0x04 0x06 0x30 0x31 0x1E 0x11 0x03 0x04 0x05 0x3A 0x3C 0x03
0x3C 0x3C 0x3C
1 1 1
0x18 0x18 0x18
0x24 0x24 0x24
0x25 0x25 0x25
0x3D 0x3D 0x3D
0x20 0x20 0x20
0x1F
0x21
0x1A18 3B34
0x21 0x33 0x21 0x18
0x38
0x3D
0x34
0x3B
0x18
0x1A
0x2120 BD38
0x24
1
0x25
0x38
1
0x3D
0x20
0x21
0x21 0x21 0x21 0x21 0x21 0x21 0x21 0x12 0x04 0x0A 0x04 0x25 0x25 0x04 0x14 0x06 0x15 0x16 0x17
0x0000 1716
0x24 0x24 0x06
Rev. 0 |
Page 17 of 20 |
August 2008
AD1989B
Table 9. Connection List (Continued)
Connections Node ID 37 38 39 3A 3C 3D [0-3] 0x0006 0403 0x0000 0011 0x0000 0014 0x0000 0015 0x0000 0017 0x0000 0012 [4-7] 0 NID I 0x03 0x11 0x14 0x15 0x17 0x12 1 NID 0x04 I 2 NID 0x06 I 3 NID I 4 NID I 5 NID I 6 NID I 7 NID
Rev. 0 |
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August 2008
AD1989B
DEFAULT CONFIGURATION BYTES
In Table 10, default configuration values are set on codec power-up only. Default configuration values are not reset by link or soft reset to preserve modifications by BIOS control. Table 10. Default Configuration Bytes
31:30 Name Value Port A (Headphone) 0x0221 4030 Port D (Front L/R) 0x0101 4010 Mono Out 0x9913 01F0 Port B (Front Mic) 0x02A1 9040 Port C (Line In) 0x0181 3021 Port F (Surr Back) 0x0101 1012 Port E (Rear Mic) 0x01A1 9020 CD IN/ Line In 0x9933 012E Analog PCBeep 0x99F3 01F0 S/PDIF_1 Out 0x0145 11F0 S/PDIF In 0x01C5 11F0 S/PDIF_2 Out 0x9856 01F0 Port G (C/LFE) 0x0101 6011 Port H (7.1) 0x0101 2014 Connectivity Jack Jack Fixed Jack Jack Jack Jack Fixed Fixed Jack Jack Fixed Jack Jack 29:28 Chassis External External Internal External External External External Internal Internal External External Internal External External 27:24 Position Front Rear Special 3 Front Rear Rear Rear Special 3 Special 3 Rear Rear Special 2 Rear Rear 23:20 Def. Device HP Out Line Out Speaker Mic In Line In Line Out Mic In CD Other S/PDIF Out S/PDIF In Digital Out Line Out Line Out 19:16 Conn Type 1/8" Jack 1/8" Jack ATAPI 1/8" Jack 1/8" Jack 1/8" Jack 1/8" Jack ATAPI ATAPI Optical Optical Other Digital 1/8" Jack 1/8" Jack 15:12 Color Green Green Unknown Pink Blue Black Pink Unknown Unknown Black Black Unknown Orange Grey 8 JD 0 0 1 0 0 0 0 1 1 1 1 1 0 0 7:4 Def Assn 3 1 F 4 2 1 2 2 F F F F 1 1 3:0 Sequence 0 0 0 0 1 2 0 E 0 0 0 0 1 4
Location
Rev. 0 |
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August 2008
AD1989B
OUTLINE DIMENSIONS
Dimensions are shown in millimeters.
7.00 BSC SQ
0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
*EXPOSED PAD
(BOTTOM VIEW)
5.25 5.10 SQ 4.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 5.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
SEATING PLANE
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 *NOTE: THE EXPOSED PAD IS REQUIRED TO BE ELECTRICALLY AND THERMALLY CONNECTED TO VSS. THIS SHOULD BE IMPLEMENTED BY SOLDERING THE EXPOSED PAD TO A VSS PCB LAND THAT IS THE SAME SIZE AS THE EXPOSED PAD. THE VSS PCB LAND SHOULD BE ROBUSTLY CONNECTED TO THE VSS PLANE IN THE PCB WITH AN ARRAY OF THERMAL VIAS FOR BEST PERFORMANCE.
Figure 3. 48-Lead, Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD1989BJCPZ1 AD1989BJCPZ-RL1
1
Temperature Range 0C to 70C 0C to 70C
Package Description 48-Lead LFCSP_VQ 48-Lead LFCSP_VQ, 13" Tape and Reel
Package Option CP-48-1 CP-48-1
Z = RoHS Compliant Part.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07547-0-08/08(0)
Rev. 0 |
Page 20 of 20 |
August 2008

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